The present invention is based on Japanese priority applications No. 2002-158997 filed May 31, 2002, No. 2002-316076 filed Oct. 30, 2002 and No. 2003-127344 filed May 2, 2003, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to semiconductor devices and, more particularly, to a semiconductor device configured to be surface-mountable and manufacturing method thereof.
2. Description of the Related Art
In recent years, high-densification of semiconductor chips has progressed remarkably, and the size of semiconductor chips has been reduced. In connection with this, high-densification and high-functionalization of semiconductor devices have progressed, and a technique has been developed to integrally incorporate a plurality of semiconductor chips into one semiconductor device. For example, there is a semiconductor device in which a plurality of semiconductor chips of different kinds and functions are connected to each other and external connection electrodes are provided.
Although there is a multi-chip module (MCM) as one example which accommodates a plurality of semiconductor chips in one package, such a conventional MCM does not have a fine structure that is the same as a semiconductor chip having a recently developed fine structure.
Japanese Laid-Open Patent Application No. 2001-217381 discloses an example of a technique to accommodate a plurality of semiconductor chips in one package. With the technique disclosed in this patent document, a plurality of semiconductor chips are arranged on a mounting jig and copper posts are formed on electrodes of each semiconductor chip. Then, the semiconductor chips together with the copper posts are encapsulated by a seal resin using transfer molding, and a surface of the seal resin is grinded so as to expose the copper posts. After forming wiring (rearrangement wiring) on the surface of the seal resin on which the copper posts are exposed, external connection electrodes are formed on the rearrangement wiring.
Japanese Laid-Open Patent Application No. 2001-332643 discloses a technique similar to that disclosed in the above-mentioned patent document. This patent document discloses formation of a protective film on a back surface of each semiconductor chip.
Additionally, Japanese Laid-Open Patent Application No. 7-86502 discloses a technique wherein a plurality of semiconductor chips are accommodated in a recess formed in a substrate and rearrangement wiring is formed on the semiconductor chips and then external connection terminals are formed on the rearrangement wiring. With this technique, the depth of the recess is so that the circuit formation surface of each semiconductor chip aligns with the surface of the substrate.
Further, Japanese Laid-Open Patent Application No. 2002-110714 discloses a technique wherein a plurality of semiconductor chips are arranged with the circuit formation surfaces facing downward and a resin is filled between the semiconductor chips while setting the circuit formation surfaces of the semiconductor chips to be a flat surface by covering the back surfaces and side surfaces of the semiconductor chips. Thereafter, rearrangement wiring is formed on the side of the circuit formation surfaces so as to form external connection terminals.
Moreover, Japanese Laid-Open Patent Application No. 5-206368 discloses a technique wherein a plurality of semiconductor chips are mounted on a thermally conductive substrate, an insulating resin is filled between the chips and rearrangement wiring is formed by aluminum on the circuit formation surfaces.
Although the above-mentioned conventional technique is constituted by mounting a plurality of semiconductor chips in a side-by-side arrangement, many kinds of stack-type semiconductor devices, in which a plurality of semiconductor chips are stacked, have been developed.
As examples of document disclosing a stack-type semiconductor device, there are Japanese Laid-Open Patent Applications No. 2001-298149 and No. 2001-320015.
With the technology disclosed in Japanese Laid-Open Patent Application No. 2001-298149, an upper semiconductor chip is mounted inside a pad area (peripheral-arranged electrodes) of a lower semiconductor chip on which the upper semiconductor chip is stacked. Additionally, with the technique disclosed in Japanese Laid-Open Patent Application No. 2001-320015, conductive pillars (column-shaped metal members) are provided on a wiring layer on each of the stacked semiconductor chips.
With the technique disclosed in the above-mentioned Japanese Laid-Open Patent Applications No. 2001-217381 and No. 2001-332643, the semiconductor chips are encapsulated by a seal resin using transfer molding, and, thus, a pressure applied during the transfer molding may have an adverse affect on the semiconductor chips. Additionally, a large force may be exerted on the semiconductor chips also at the time of grounding of the seal resin surface after molding. Further, when the semiconductor chips are stacked, warp may occur due to contraction at the time of curing the seal resin on a mounting substrate (silicon wafer). Such a warp may have an adverse affect when the semiconductor chips are stacked.
Laid-Open Patent Application No. 7-86502, a high accuracy is required in the depth of the recess when forming the recess which accommodates semiconductor chips. Particularly, if the semiconductor chips become thin, a higher accuracy is required in the depth of the recess, which may be difficult to achieve.
Further, with the technique disclosed in Japanese Laid-Open Patent Application No. 2002-110714, a resin is provided on the back side of semiconductor chips, which causes a problem of poor heat radiation characteristic of the semiconductor chips. Moreover, warpage may occur in the semiconductor device due to the resin being cured on the back side of the semiconductor chips.
Moreover, according to the technique disclosed in Japanese Laid-Open Patent Applications No. 2002-110714 and No. 5-206368, a resin is filled between semiconductor chips after arranging the semiconductor chips at predetermined positions, and, thus, there may be a case in which a displacement of the semiconductor chips occurs when mounting the semiconductor chips or filling the resin. With this technique, it is impossible to remove the displaced chip.
Further, with respect to stacked type semiconductor device, in the technique disclosed in Japanese Laid-Open Patent Application No. 2001-298149, an upper semiconductor chip is mounted inside the pad area (peripheral arrangement electrode) of the lower semiconductor chip on which the upper semiconductor chip is stacked, semiconductor chips having the same size cannot be stacked. Moreover, with the technique disclosed in Japanese Laid-Open Patent Application No. 2001-320015, the manufacturing cost of a semiconductor device is increased due to the formation of the conductive pillars.
In the meantime, a semiconductor device which is formed by stacking semiconductor chips, generally the semiconductor chip is securely fixed to a substrate by covering the circumference of the semiconductor chip. Additionally, in a case where a plurality of semiconductor chips are mounted on a substrate such as a multi-chip module, a resin is filled between the semiconductor chips as disclosed in Japanese Laid-Open Patent Application No. 2002-110714. With such a filled resin layer, each semiconductor chip can be securely fixed to the substrate, and the semiconductor chips are insulated to each other.
The filled resin layer can be previously formed prior to mounting the semiconductor chips onto the substrate, or the resin may be filled after mounting the semiconductor chips onto the substrate.
When the above-mentioned filled resin layer is formed prior to mounting the semiconductor chip, a part of the filled resin layer formed on the substrate is removed so as to form an opening in which the surface of the substrate is exposed, and the semiconductor chip is mounted by being placed in the opening. Accordingly, the opening is formed with a size slightly larger than the outer configuration of the semiconductor chip.
Additionally, there is a method of forming the filled resin layer after the semiconductor chip is mounted, in which a resin is cured after being applied onto the substrate on which the semiconductor chip is mounted and masked. Also in this case, it is difficult to tightly contact the filled resin layer with the side surfaces of the semiconductor chip, and a gap may be formed between the filled resin layer and side surfaces of the semiconductor chips.
If such a gap is formed between the filled resin layer and the side surfaces of the semiconductor chip, a sufficient fixation effect to the semiconductor chip by the filled resin layer cannot be achieved. Additionally, such a gap may be an obstacle for formation of wiring on the semiconductor chip and the filled resin layer. When a insulating resin layer is formed on the semiconductor chip and the filled resin layer, the insulating resin enters the gap and the gap is filled by the insulating resin in the step of forming the insulating resin layer. However, the entire gap cannot be filled with the insulating resin.
It is a general object of the present invention to provide an improved and useful semiconductor device in which the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide a semiconductor device and manufacturing method thereof in which circuit formation surfaces of each of a plurality of semiconductor chips can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified.
Another object of the present invention is to provide a semiconductor device and a manufacturing method thereof in which semiconductor chips having the same size can be easily stacked with a thin wiring layer formed therebetween.
Another object of the present invention is to provide a semiconductor device and manufacturing method thereof in which a filled resin layer tightly contact with side surfaces of a semiconductor chip.
In order to achieve the above-mentioned object, there is provided according to one aspect of the present invention a semiconductor device, comprising: a plurality of semiconductor elements mounted on a substrate via an adhesive layer in a two-dimensional arrangement; a resin layer formed on the substrate and located around the semiconductor elements, the resin layer having substantially the same thickness as a thickness of the semiconductor elements; an organic insulating layer formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements; a rearrangement wiring layer formed on the organic insulating layer and electrodes of the semiconductor chips; and external connection terminals electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.
There is provided according to another aspect of the present invention a manufacturing method of a semiconductor device which packages a plurality of semiconductor elements, comprising the steps of: forming a resin layer having a thickness equal to a thickness of the semiconductor elements to be mounted; forming openings in the resin layer by partially removing the resin layer; locating the semiconductor elements within the openings, respectively, with circuit formation surfaces facing upward; forming an organic insulating layer over a surface of the resin layer and the circuit formation surfaces of the semiconductor elements; forming a rearrangement wiring layer on the organic insulating layer and electrodes of the semiconductor elements; and forming external connection terminals on the rearrangement wiring layer, the external connection terminals being connected to the electrodes of the semiconductor elements through wiring in the rearrangement wiring layer.
According to the above-mentioned invention, the circuit formation surfaces of the semiconductor elements and the surface of the resin layer are located substantially in the same plane (substantially at the same level) since the thickness of the resin layer surrounding the semiconductor elements is substantially equal to the thickness of the semiconductor elements. Thus, the rearrangement wiring layer can be easily formed on the semiconductor elements.
Additionally, there is provided according to another aspect of the present invention a stacked semiconductor device comprising a plurality of layer structures stacked one on another, each of the layer structure comprising: a semiconductor element arranged on a substrate via an adhesive layer; a resin layer formed on the substrate and surrounding the semiconductor element, the resin layer having a thickness substantially equal to a thickness of the semiconductor element; an organic insulating layer formed over a surface of the resin layer and a circuit formation surface of the semiconductor element; and a rearrangement wiring layer formed on the semiconductor element and electrodes of the semiconductor element.
Additionally, there is provided according to another aspect of the present invention a manufacturing method of a stacked semiconductor device, comprising the steps of: forming a first resin layer on a substrate, the first resin layer having a thickness substantially equal to a thickness of a first semiconductor element to be mounted, the first resin layer surrounding the first semiconductor element; forming a first opening in the first resin layer so that the first semiconductor element is located in the first opening; locating the first semiconductor element in the first opening; forming a first organic insulating layer over a surface of the first resin layer and a circuit formation surface of the first semiconductor element; forming a first rearrangement wiring layer on the first organic insulating layer and electrodes of the first semiconductor element; forming a second resin layer on the first rearrangement wiring layer, the second resin layer having a thickness substantially equal to a thickness of a second semiconductor element to be mounted, the second resin layer surrounding the second semiconductor element; forming a second opening in the second resin layer so that the second semiconductor element is located in the second opening; locating the second semiconductor element in the second opening; forming a second organic insulating layer over a surface of the second resin layer and a circuit formation surface of the second semiconductor element; forming a second rearrangement wiring layer on the second organic insulating layer; electrically connecting the first rearrangement wiring layer to the second rearrangement wiring layer by forming conductive connection parts extending through the second resin layer between the first rearrangement wiring layer and the second rearrangement wiring layer.
According to the above-mentioned invention, the circuit formation surfaces of the semiconductor elements and the surface of the resin layer are located substantially in the same plane (substantially at the same level) since the thickness of the resin layer surrounding the semiconductor elements is substantially equal to the thickness of the semiconductor elements. Thus, the rearrangement wiring layer can be easily formed on the semiconductor elements. Additionally, since the rearrangement wiring layers extend to the surface of the resin layer, electrical connection between the rearrangement wiring layers can be easily achieved by conductive connection parts such as vias.
Additionally, there is provided according to another aspect of the present invention a semiconductor device comprising: a substrate; a semiconductor element mounted on the substrate; and a resin layer provided around the semiconductor element and having an upper surface substantially at the same level with an upper surface of the semiconductor element, wherein the resin layer is a half-curable resin having a characteristic that the resin is softened and fluidized when heated in a half-cured state, and the resin layer is in close contact with side surfaces of the semiconductor element with no gap formed therebetween.
Additionally, there is provided according to another aspect of the present invention a manufacturing method of a semiconductor device, comprising the steps of: forming a resin layer of a half-cured state on a substrate so that a semiconductor element is positioned in the resin layer, the resin layer made of a half-curable resin;
fluidizing the filing resin layer of the half-cured state by heating; eliminating a gap between the semiconductor element and the filing resin layer by filling the fluidized filing resin layer in the gap; and completely curing the resin layer by heating.
According to the above-mentioned invention, by using the half-curable resin as a material of the resin layer, a gap between the semiconductor element and the resin layer can be filled by the softened and fluidized resin layer. Thus, a semiconductor device having no gap between the semiconductor element and the resin layer can be easily manufactured.
Additionally, there is provided according to another aspect of the present invention a manufacturing method of a semiconductor device, comprising the steps of: forming a resin layer having an opening on a substrate and preparing a semiconductor element provided with an adhesive formed of a half-curable resin; locating the semiconductor element in the opening; pressing the semiconductor element onto the substrate via the adhesive while fluidizing the adhesive of the half-cured state by heating; and curing the adhesive by heating while maintaining the semiconductor element at a position where an upper surface of the semiconductor element lies substantially in the same plane where an upper surface of the filing resin layer lies.
Additionally, there is provided according to another aspect of the present invention a manufacturing method of a semiconductor device, comprising the steps of: forming a resin layer having an opening on a substrate and preparing a semiconductor element provided with an adhesive; locating the semiconductor element in the opening by supporting an upper surface of the semiconductor element by a bottom surface of a bonding tool; and curing the adhesive in a state where the bottom surface of the bonding tool is in contact with an upper surface of the resin layer.
According to the above-mentioned invention, a gap between the semiconductor element and the resin layer can be filled by the adhesive, and the upper surface of the semiconductor element and the upper surface of the filing resin layer can be accurately set substantially in the same plane. Additionally, since an appropriate amount of adhesive is applied and the adhesive fills the gap by being pressed by the semiconductor element. Thus, the adhesive can be brought into close contact with the substrate and insufficient wet or a climbing up phenomenon of the adhesive can be prevented.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.